A variety of ultra high sample rate analog to digital converter (ADC) configurations are known. However, some of these include components that unnecessarily increase the size and complexity of particular configurations. For example, in ultra high sample rate ADC applications taking samples in the 1-10 gigahertz range, for example, above 3 GHz, interface connections for transmitting the data from a sampling location to a processing location has required complicated serializing and framing circuitry. Further, some ultra high sample rate ADC configurations have unacceptable pin counts, power consumption, data latency, silicon area, high non-recurring engineering costs, and other costs.